Waseem Arshad

 


 

Research Work

Recently I have had the experience to tape-out a chip. I have completed the IC design cycle from specifications to post layout simulations and then tape-out. I have designed two novel circuits for Voltage Controlled Delay Lines having linear to be used in Delay locked loop at 2 GHz. I have also worked on the layout of the DLL for tape-out. I also have designed high gain amplifiers.

Contact Information :


Waseem Arshad
Researcher
Analog Mixed Signal Group
NUST-SEECS
waseem.arshad@seecs.edu.pk