I believe in innovation and that the way you get innovation is you fund research and you learn the basic facts. (Bill Gates)





Research Work

I received my bachelors degree in Electronics Engineering form SEECS NUST in 2010 and MS degree in Electrical Engineering from the same institute in expected to be completed in 2013. I have served as Research Engineer at Analog and Mixed Signal Group (AMSG) at SEECS NUST. At AMSG I have used IHP SGB25H3 250nm technology for a high speed Gm-C integrator design which was used in delta sigma part of Switched Mode Transmitter Architecture. As a part of my MS thesis I have been involved in the project titled :" Power and Area Efficient Implantable Biomedical micro-chip design using wireless power and data telemetry". My job in this project is to design the low noise, low area and low power neural signal acquisition interface in NCSU AMI06 technology. I am also working on the wireless data and power telemetry part of the project.



"Neural Recording and Stimulation Frontend Design for Brain Machine Interface Microchip"

Timeline: March 2012-May 2013

Project Overview

Recording neural data has been of prime interest for neural scientist and clinicians since it can help demystify the precise functionality of the brain and work out numerous brain related ailments. Traditionally the modes of neural data recording are error prone and infectious. But now, thanks to the advances in wireless data and power telemetry, more accurate invasive modes of data recording can be used. In these methodologies wirelessly powered microchips are placed beneath the skin and a telemetric connection has to be established between the chip and the external module. The chip must consume least amount of power because just a 1 degree increase in temperature of the chip can burn down the tissues from which we are to collect data. Area is another tight constraint for the implants and finally the analog interface needs to have very low input referred noise to process neural signals, notably action potentials, which could be as low as a few micro-volts.

Like diagnosing neural disorders and demystifying brain functionality, another important requirement from the biomedical micro-chip implants is to help build prosthetic devices for amputated persons. This requirement translates to the efficient and robust designing of stimulating path in the neural analog front end.

Block Level Diagram of the Entire Project

Below is the block diagram of telemetry powered bio implantable microchip. The brownish center layer represents skin, right the microchip and on left we have the external module. My part in this project was to design neural recording and stimulation interface for the microchip, blocks encircled by the red line. Neural recording demands acquisition of neural signals, their amplification/filtering and digitization. Stimulation requires conversion of digital code ,obtained from digital controller, into a neural spike.


Neural Interface Specifications

Some of the key specifications of the neural interface are elaborated below. These specifications were further narrowed down to circuit level specifications using stare-of-the-art and system level modelling. 1) Power consumption: 60uW (neural amplifier, ADC, stimulator) 2) Area: 0.6mm^2 3) No of channels: 8 4) Technology: 0.5um nwell 5) Noise Efficiency Factor < 5 and 6) Gain and bandwidth of filter amplifier must be programmable

Neural Interface Block Level Diagram

Conventionally a high power and area neural signal amplifiers are assigned to each channel for amplification and filtering and then some of the signals are multiplexed so that fewer ADCs could be used. I have worked on a new architecture in which the front end's components were shuffled to conserve the minimum possible area. Similarly low power techniques were used for circuit designing to make the system power efficient while maintaining acceptable Noise Efficiency Factor (NEF).

Neural Interface Layout

This is the layout of eight channel prototype and contains recording path (neural signals amplifier and SAR ADC) and the stimulating path consisting of 8 stimulators.


Selected Layout Results

Some of the post layout simulation results are explained below:

Neural filter amplifier settling time: 1us

Gain Tunability Range: 40-60dB

Bandwidth Tunability Range: 100mHz-9KHz

Noise Efficiency Factor: 4.1

Power Consumption (Filter Amplifier+SAR ADC): 77uW

Area Consumption (Filter Amplifier+SAR ADC):0.407mm2

"Gm-C Integrator Design for Delta Sigma Modulator"

Timeline: Jan 2011-Sep 2011

Project Overview

The main bottleneck in the continuous time transmitter architecture is its power consumption as it is made adaptable to multiple standards. Adaptability demands higher bandwidth which in turn requires high current consumption, shooting up the power consequently. The idea of this project was to develop a power efficient switched mode prototype of a transmitter architecture by designing a Switched Mode Power Amplifier (SMPA). Now the switched mode power amplifier would need a digitally modulated signal to be driven unlike continuous time power amplifiers. We designed one such Delta Sigma Modulator (DSM) to drive the SMPA and I had been working on designing integrator part of the DSM. I did system level modelling of the DSM in verilog A and designed single ended folded cascode integrator at 50MHz. Integrator schematic is shown below.



Sami ur Rehman, A. M. Kamboh "A New Architecture for Neural Signal Amplification in Implantable Brain Machine Interfaces", Proceedings of the 35th Annual International Conference on IEEE Engineering in Medicine and Biology Society (IEEE EMBS), July 2013, Osaka Japan.

Sami urRehman, A. M. Kamboh "A Power and Area Efficient 8-Channel Neural Signal Front End for Biomedical Applications ", Proceedings of 2013 2nd International Conference on Solid-State and Integrated Circuit (ICSIC 2013), April 2013, Vancouver, Canada.

Sami urRehman, Mehwish Zahra, Abdullah Mansoor , "Delta sigma based novel modulation technique replacing analog amplitude modulation (AM)," ", Proceedings of the 8th Annual International Conference on IEEE High Capacity Optical Networks and Enabling Technologies (HONET), Dec. 2011 Riyadh, Saudi Arabia.

Sami urRehman, Muhammad Ali Khalid "Switched mode transmitter architecture using low pass delta sigma modulator," Proceedings of the IEEE 7th International Conference on Emerging Technologies (ICET), September 2011, Islamabad Pakistan.

Contact :

Research Engineer
Analog Mixed Signal Group

+92 346 5347579