AMSG Summer Internship

The School of Electrical Engineering and Computer Sciences (SEECS) is arranging a 4 weeks long internship program during the Summer 2010 consisting of workshops on different design and analytical aspects of Analog/Mixed Signal Integrated Circuit (IC) designing and High Frequency Circuits. During the course of the program, the participants will learn both the theoretical and the practical aspects of the design.

AMSG Summer School 2010


    12th - 17th July     Workshop 1 (Operational Amplifier)
    19th - 23th July     Workshop 2 (Cadence based IC Design Cycle)
    26th - 30th July     Workshop 3 (Sigma Delta ADC's)
    2nd - 6th August     Workshop 4 (Introduction of RF Microelectronics)
Timings: 9:30 AM - 1: 00 PM Monday - Friday


Workshop 1 (Operational Amplifier):

Operational Amplifier (Op-Amp) is one of the most critical blocks in Analog IC's and is found in almost each one of them. Because of its critical nature, the overall performance of the system greatly depends on the performance of the Op-Amp. A careful analytical approach coupled with the sound knowledge about its theoretical background is the key to designing an Op-Amp that can fulfill the requirements of the system.
Workshop Contents:
  • Op-Amp Basics (Design parameters, Performance parameters, the trade-off among the design and performance parameters and their dependence on each other)
  • The Analytical Aspects and extraction of parameters for Op-Amp Designing.
  • Biasing Techniques and circuits for Op-Amps.
  • Loading Types (Different types of loads for Op-Amps and their differences, how do they affect the load driving capabilities of Op-Amps?)
  • Example (Op-Amp Design with a complete biasing circuitry)

Workshop 2 (Cadence based IC Design Cycle)

Cadence is an industry standard tool for IC designing which is being used throughout the world in both academia and industry, for educational, research and business purposes. An IC designer needs to be aware of it and also the complete design cycle that must be followed in order to make a chip.
Workshop Contents
  • Top-Down Design methodology for IC design
  • System Level Design on Matlab/Simulink
  • Behavioral Analysis using Verilog-A
  • Transistor level designing
  • Integrating and Simulating Components
  • Layout
  • Post-Layout

Workshop 3 (Sigma Delta Analog to Digital Converter (ADC)):

Sigma Delta (ΣΔ) ADC’s are popular for converting Analog signals into the Digital ones while maintaining a high resolution. The sampling of the signal takes place at a much higher rate which relaxes the otherwise stringent requirements for the Analog circuitry. They find applications in communication systems, instrumentation and control systems and biomedical applications.
Workshop Contents
  • Sigma Delta Principal of Operation
  • Building Blocks and their specifications
  • System Level Design on Matlab and parameters extraction
  • Implementation on Cadence
  • Simulations

Workshop 4 (Introduction of RF Microelectronics):

Nanometer scale IC design is a high demand research area. Technology scaling defined by Moore's law has brought many new challenges in the area of IC design. At the same to cope with the demand of high speed wireless communications lot of research is needed in the area of RF IC design. AMSG is also engaged in research in this topic. The purpose of this one workshop is introducing basic concepts involved in RF IC Design. This workshop will serve as the pre-requisite for comprehensive RF Tranceiver design course which will be offered in Fall 2010.
Workshop Contents:
  • Analog and Digital Communications
  • Analog and Digital Modulation
  • Analog Transmitter and Receiver Architectures
  • Noise Figure, Phase noise, and Intersymbol Interference
  • Linearity, Cross Modulation and Intermodulation Products


Registration:



Registration is closed now. We will organize similiar activity again in future. Keep in touch!

Workshop fee:

Professionals:
        Rs.20,000/- (Rs. 5,000/- Per Workshop)


Enrolled NUST Students:
        Rs. 8,000/- (Rs. 2,000/- Per Workshop)
All participants are required to submit Registration fee through Bank Draft. Pay Order should be in favour of "SEECS Consultancy Fund" Account #22927000074501, Habib Bank Limited, NUST, H-12 Islamabad. The Bank Draft or Pay Order must reach SEECS Information Office (by hand or through courier) before 1st July, 2010

Prerequisites:

Participants of Workshop 1,3, and 4 must have done atleast Electronics I and Electronics II undergraduate level courses.

For queries, contact:             Abdullah Mansoor
                                             abdullah.mansoor@seecs.edu.pk


                                            Saifullah Amir
                                             saifullah.amir@seecs.edu.pk


                                             Tel: +92-51-9085-2400,+92-51-9085-2133, +92-51-9085-2139
                                             Fax: +92-51-8317-363